1. Field of the Invention
The present invention relates to a process for producing a semiconductor device having fine contact plugs.
2. Description of the Related Art
In recent years, as semiconductor devices have become fine, the diffused layers formed in the semiconductor substrate have become fine as well. In this connection, the contact plugs electrically connecting these fine diffused layers with electrodes are becoming increasingly fine.
Contact plugs have heretofore been formed by forming contact holes in the inter-layer insulating film formed on a semiconductor substrate so as to reach the diffused layers formed in the semiconductor substrate and then filling each contact hole with a conductive material. However, as the contact holes become fine, the patterning therefore becomes very difficult when the diameter of hole is 1 .mu.m or less. Hence, it is generally conducted to once form each contact hole so as to have a diameter slightly larger than actually required and then form, on the inner surface of the contact hole, a side wall made of an insulating material (e.g. silicon oxide) by CVD (chemical vapor deposition) to form fine contact holes.
In such a memory device as a storage electrode is formed above each bit line, each capacitor contact plug is present between bit lines. In order to prevent the short-circuiting between capacitor contact plug and bit lines, it is generally conducted to (1) cover the circumference of each bit line with an insulating film having an etching rate different from that of inter-layer insulating film, or (2) form an insulating film on the inner surface of each opening (each contact hole) for formation of capacitor contact plug and then fill each contact hole with a conductive material.
A conventional method for formation of fine contact plugs is described below on a case of forming a stack type capacitor of the memory cell region of DRAM, referring to FIGS. 5(a)-5(g) and FIGS. 6(a)-6(e).
First, as shown in FIG. 5(a), on a semiconductor substrate 1 having, at given positions, element-insulating regions 2 made of a silicon oxide film is formed a gate oxide film (not shown) by a thermal oxidation method or the like; then, on the whole surface of the resulting material is formed an impurity-containing polysilicon film; the polysilicon film is subjected to patterning; thereby, gate electrodes 3 are formed.
Successively, as shown in FIG. 5(b), ion implantation is conducted to form diffused layers 4; then, on the whole surface of the resulting material is formed a first inter-layer insulating film consisting of a BPSG film (a boron-phosphorus-silica glass film) or the like.
Next, as shown in FIG. 5(c), bit contact holes 6 are formed so as to reach the diffused layers 4; successively, as shown in FIG. 5(d), an insulating film 7 is formed, by CVD, on the first inter-layer insulating film 5 including the inner surface of each bit contact hole 6. The CVD insulating film 7 is etched back to form each side wall 8, as shown in FIG. 5(e).
A film made of a conductive material is formed so as to fill each bit contact hole 6 having a side wall 8; patterning is conducted; thereby, bit contact plugs 9 and bit lines 10 are formed as shown in FIG. 5(f). Then, on the whole surface of the resulting material is formed a second inter-layer insulating film 11 consisting of a BPSG film or the like, and thereon is formed an insulating film 12 [FIG. 5(g)].
Next, as shown in FIG. 6(a), capacitor contact holes 13 are formed so as to reach the diffused layers 4; then, as shown in FIG. 6(b), an insulating film 14 is formed, by CVD, on the insulating film 12 and the inner surface of each capacitor contact hole 13. Successively, the CVD insulating film 14 is etched back to form each side wall 15, as shown in FIG. 6(c).
A film made of a conductive material is formed so as to fill each capacitor contact hole 13 having a side wall 15; patterning is conducted; thereby, each capacitor contact plug 16 and each storage electrode 17 are formed as shown in FIG. 6(d).
Then, a capacitor insulating film (not shown) is formed. Thereon is formed an impurity-containing polysilicon film 18 for formation of plate electrode, whereby a capacitor structure is formed. Thereon is formed a third inter-layer insulating film (not shown), after which other constituents such as upper wiring and the like (not shown) are formed.
In the above conventional constitution, however, each side wall consisting of a CVD insulating film makes direct contact with the surface of a semiconductor substrate, which caused formation of GR center (generation-recombination center) to generate leakage current. This generation of leakage current particularly in the capacitor contact plugs of memory circuit is a very serious problem because it makes difficult the securement of a sufficient capacity in the current situation in which semiconductor devices are becoming increasingly fine.